16-Bit MAC Unit Design

Overview

This project focuses on designing a high-performance 16-bit Multiply-Accumulate (MAC) unit. The design utilizes Vedic multiplication techniques for fast computation and optimized addition through Carry Save Adders (CSA). The implementation targets enhanced performance metrics such as minimized delay, area, and power consumption.

Design Methodology

The project employed the following steps:

1. Vedic Multiplication: Leveraged the Urdhva Tiryakbhyam sutra for high-speed multiplication, breaking the computation into smaller modules (4-bit multipliers).
2. Optimized Addition: Used Carry Save Adders (CSA) to reduce propagation delay in the accumulation process.
3. RTL Implementation: Developed the Verilog code to integrate the modules.
4. Synthesis and Physical Design: Utilized Cadence tools:
   • Genus: For RTL synthesis, constraint handling, and timing optimization.
   • Innovus: For place and route, clock tree synthesis, and final GDSII file generation.

Tools and Technologies

• Languages: Verilog HDL
• EDA Tools: Cadence Genus (Synthesis), Cadence Innovus (Physical Design)
• Mathematical Techniques: Vedic Multiplication, Carry Save Adder

Results

The project achieved the following results:

• Optimized delay, area, and power consumption.
• Efficient multiplication and accumulation for 16-bit inputs.
• Final GDSII file generation with complete physical design.